Scheduling Semiconductor Wafer Fabrication

This paper is concerned with assessing the impact that scheduling can have on the performance of semiconductor wafer fabrication facilities. The performance measure considered here is the mean throughput time (sometimes called cycle time, turnaround time or manufacturing interval) for a lot of wafers. A variety of input control and sequencing rules are evaluated using a simulation model of a representative but fictitious semiconductor wafer fab. Certain of these scheduling rules are derived by restricting attention to the subset of stations that are heavily utilized, and using a Brownian network model, which approximates a multiclass queueing network model with dynamic control capability. Three versions of the wafer fab model are studied, which differ only by the number of servers present at particular stations. The three versions have one, two and four stations, respectively, which are heavily utilized (near 90-percent utilization). The simulation results indicate that scheduling has a significant impact on average throughput time, with larger improvements coming from discretionary input control than from lot sequencing. The effects that specific sequencing rules have are highly dependent upon both the type of input control used and the number of bottleneck stations in the fab. I . INTRODUCTION HIS PAPER is concerned with assessing the impact T that scheduling can have on the performance of semiconductor wafer fabrication facilities. The performance measure considered here is the mean throughput time (sometimes called cycle time, turnaround time, or manufacturing interval) for a lot of wafers. A variety of input control and lot sequencing rules are evaluated using a simulation model of a representative but fictitious semiconductor wafer fab. The fab uses a single process technology, which requires 172 total operations at 24 different single or multiserver stations. Three versions of the model, which differ only by the number of servers present at particular stations, are used. The three models have one, two, and four stations, respectively, that are heavily utilized (near 90-percent utilization). Four different types of input mechanisms are considered and different sequencing rules are evaluated for each. The four types are Poisson input, deterministic input (interamval times are constant), closed loop input (the number of lots in the system is held constant), and a policy we call workload regulating input, which releases a lot of wafers into the system whenever the total amount of remaining work in the system for any bottleneck station falls Manuscript received April 11, 1987; revised March 15, 1988. This work was supported in part by the Semiconductor Research Corporation under Grant 84-01-046 (Manufacturing Science for VLSI, Center for Integrated Systems, Stanford University). The author is with the Sloan School of Management, M.I.T., Cambridge, MA 02139. IEEE Log Number 8821558. below a prescribed level. The lot sequencing decisions consist of dynamically choosing which of the lots queued at a particular station should be processed next. The workload regulating input policy and certain sequencing rules are derived or suggested by restricting attention to the subset of stations that are heavily utilized, and using a Brownian network model, which approximates a multiclass queueing network with dynamic control capability. By superimposing an objective function on the Brownian network model, various control problems can be formulated. The solutions to these problems yield effective input control and sequencing rules for the heavily utilized subnetwork, and these rules are then tested in the simulation model of the entire fab. Interested readers are referred to [8] for a development of the Brownian network model, and to [20], [9] for solutions to various Brownian network control problems that led to some of the scheduling rules tested in this paper. The simulation results indicate that scheduling has L significant impact on the performance of semiconductor wafer fabrication, with larger improvements coming from discretionary input control than from lot sequencing. In particular, deterministic, closed loop and workload regulating input provided improved performance over Poisson input, by substantially reducing both the mean and variability of throughput times. Queueing theory results (see [2], [21], and [ 2 3 ] ) predict that reducing the variability in the input will improve performance. However, it is very encouraging to observe the size of the impact on overall performance (35-45 percent reduction in average total queueing time) that can be gained by properly regulating the input. However, the improvements resulting from lot sequencing rules were quite modest (less than 10-percent reduction in average total queueing time). Moreover, the effects that specific sequencing rules have are highly dependent upon both the type of input control used and the number of bottleneck stations in the fab. The remainder of this paper is organized as follows. Section I1 summarizes the relevant literature on both wafer fabrication and job shop scheduling. Section I11 describes the simulation model that was developed to examine different scheduling rules in the wafer fab environment, and the structure of the simulation study is laid out in Section IV. In Section V, the results of the simulation study are presented and discussed, and the conclusions of the study are contained in Section VI. The Appendix contains a brief description of the theoretical origins of cer ain scheduling rules that are considered in this study. 0894-6507/88/0800-0115$01 .OO